The present invention relates to a semiconductor integrated circuit, such as an LSI circuit, and more specifically to an LSI circuit with a plurality of internal power supplies, which is adapted for a semiconductor memory device by way of example.
LSI circuits having more than one internal power supply include DRAMs employing a negative word line (NWL) driving technique. An example of an NWL driving technique is described in an article entitled "Circuit Design Techniques for Low-Voltage Operating and/or Giga-Scale DRAMs" by Tadato Y. et al., ISSCC Digest of Technical Papers, pp. 248-249, 1995.
This NWL technique has been proposed to meet low supply voltage requirements of DRAMs. A part of the circuit arrangement of a DRAM that employs the NWL driving technique is shown in FIG. 1. FIG. 2 shows exemplary waveforms of potentials on word and bit lines.
Although a large number of memory cells each consisting of a transistor Q and a capacitor C is arranged in rows and columns, only one memory cell is illustrated in FIG. 1. WL denotes a word line, which is connected to the gate of transistor Q in the memory cell. BL and /BL denote paired bit lines. The bit line /BL is connected to the drain of the transistor Q. WLD denotes a word line driver. SA denotes a sense amplifier. SAD denotes a sense amplifier driver.
In FIG. 2, solid lines indicate potentials on the word line WL and the paired bit lines BL and /BL. For comparison, a dashed line indicates a word line driving waveform in a DRAM in which no NWL driving technique is used.
As shown in FIG. 2, in the NWL driving technique, the potential on the word line WL in the non-selected state is a low potential VLL, which is lower than 0 V (VSS), i.e., the low level potential of the bit lines (the low level "L" of the sense amplifier SA). Thereby, a negative bias voltage is applied between the gate and source of the transistor Q, suppressing cut-off current and consequently enhancing information holding capability.
The potential on the word line WL in selected state is a high potential VHH, which is set Vth+.alpha. higher than the high-level potential of the bit line (the high level of the sense amplifier; the supply voltage VCC in this example). Vth denotes the threshold voltage of the transistor Q. Namely, the high potential VHH is set more than Vth higher than the high-level potential of the bit line. Thus, the potential on the bit line BL or /BL is fully transferred to the capacitor C.
As described above, in the NWL-based DRAM, a row decoder (not shown) for driving the word lines WL uses the negatively boosted voltage VLL and the positively boosted voltage VHH. These boosted voltages VLL and VHH are produced by internal power supply circuits built into a DRAM chip. However, when the boosted voltages VLL and VHH are produced by internal power supply circuits built into a DRAM chip, the following problems may arise at the time of turning on the power.
That is, at power-on time, the internal signal potential is either midway between VCC and VSS or in transition. In this state, not only charge/discharge currents but also through-currents flow through internal CMOS logic circuits, increasing current dissipation.
If, in this state, the VHH power supply circuit cannot compensate for through-currents in a CMOS circuit serving as the row decoder, the boosted voltage VHH will not reach the specified voltage. Thus, the VHH power supply circuit needs to have a current supply capacity great enough to compensate for through-currents that flow at power-on time. Usually, the same holds true for the VLL power supply circuit. In addition, it is required that the current supply capacity be balanced between the VHH and VSS power supply circuits.
If such requirements are not met, simultaneously operating the VHH and VSS power supply circuits at power-on time causes a phenomenon in which one of the supply voltages which is produced by a power supply circuit smaller in current supply capacity than the other rises or falls abnormally.
FIG. 3 shows a situation where the output voltage VLL of the VLL power supply circuit rises abnormally when the power is turned on.
It is expected that the boosted voltage VHH is higher than the external supply voltage VCC and the boosted voltage VLL is lower than 0 V (VSS). In a state contrary to this expectation, problems often arise in the operation of the row decoder using internal boosting power supply circuits and current dissipation increases. If the internal power supply circuit cannot accommodate the current dissipation, then the internal supply voltage further increases or decreases. That is, a vicious cycle of an increase in current dissipation and an increase or decrease in internal supply voltage is caused.
A Vt CMOS technique is known which suppresses the cutoff current of MOS transistors in CMOS logic circuits to attain a reduction in their standby current by controlling the backgate voltage of the MOS transistors.
In the conventional Vt CMOS technique, CMOS circuits connected between VCC and VSS nodes are arranged, as shown in FIG. 4, such that NMOS transistors have their sources connected to the external supply voltage VSS and their backgates connected to the internal boosted supply voltage VLL and PMOS transistors have their sources connected to the external supply voltage VCC and their backgates connected to the internal boosted supply voltage VHH.
As shown in FIG. 5, the CMOS inverters are set such that the voltages VHH and VLL in standby state are respectively set higher and lower than in active state. Thus, in the standby state the backgate of each of the NMOS and PMOS transistors becomes biased deeply, which allows the threshold voltage of each transistor to be increased and the standby current to be reduced.
As described above, the conventional DRAMs having more than one internal power supply circuits have a problem that difficulties are involved in producing internal supply voltages with stability at the time of turning on the power.